Search - verilog uart

[VHDL-FPGA-Verilog] uart

Description: 串口verilog源代码 uart code verilog-uart code verilog
Platform: | Size: 1553408 | Author: YesterDAY | Hits:

[LabView] verilog-uart-master

Description: Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
Platform: | Size: 57344 | Author: kimluan | Hits:

[VHDL-FPGA-Verilog] uart_test

Description: 基于FPGA 的sparten-6 AX-309片内串口uart通信例子(FPGA sparten-6 AX-309 uart connection example)
Platform: | Size: 386048 | Author: 小也先生 | Hits:

Description: 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
Platform: | Size: 2048 | Author: 叶古 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 嵌入式串口通讯，采用verilog编写，在altera开发板上运行(Embedded serial communication, written using Verilog, altera development board on the run)
Platform: | Size: 2843648 | Author: 歪歪mao | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilog IO模拟串口,用IO模拟uart进行串口通讯，无需硬件串口(Verilog io analog serial port, using io simulation UART serial communication, no hardware serial port)
Platform: | Size: 1276928 | Author: yt14212 | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART 功能模块，Verilog，简单实用(UART function module, Verilog, simple and practical)
Platform: | Size: 1024 | Author: pwy122 | Hits:

[Com Port] FPGA实现串口解析

Description: 用verilog语言不同的编写方式来实现各种复杂串口通讯(use the verilog to uart)
Platform: | Size: 5120 | Author: huihui2113 | Hits:

[Embeded-SCM Develop] UART

Description: 使用verilog实现串口通信功能，modesim仿真成功(Using Verilog to achieve serial communication function, modesim simulation success)
Platform: | Size: 2048 | Author: 农村小伙 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用Verilog实现的全局异步接收发送机，在quartus平台测试成功。(Use Verilog implementation of global asynchronous receive transmitter in quartus platform test successfully)
Platform: | Size: 283648 | Author: 莫五张 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于verilog的fpga串口通信,rx,tx.两根线(Basend on verilog fpga uart tong xin)
Platform: | Size: 4001792 | Author: 巴拉望 | Hits:

[Windows Develop] UART

Description: UART loopback测试实例，接收PC端发送的UART数据，原数据返回给PC端，即loopback功能(The UART loopback test instance receives the number of UART sent by the PC side According to the original data returned to the PC side, that is, the loopback function)
Platform: | Size: 6258688 | Author: 航天梦 | Hits:

[VHDL-FPGA-Verilog] UART-master

Description: FPGA Based UART in Verilog
Platform: | Size: 4096 | Author: lsyy | Hits:

[Other] Verilog_uart

Description: 锆石科技用Verilog实现uart通信，文件包括模块和顶层文件，直接解压缩在quartus上编译即可。(Zircon technology Verilog with uart communication, the file includes the module and the top file, the direct decompression can be compiled on the quartus.)
Platform: | Size: 10853376 | Author: zhengtaiyige | Hits:

[VHDL-FPGA-Verilog] UART1

Description: 基于Verilog的串口RS232控制器(RS232 controller of serial port based on Verilog)
Platform: | Size: 13188096 | Author: 拂晓神剑 | Hits:

[e-language] uart-master

Description: verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
Platform: | Size: 3072 | Author: Maren | Hits:

[Com Port] uart

Description: 一个具有固定波特率的 UART 串口收发器，可以实现串口收发器，可以实现 9600 波特率的串口通信，能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC serial port, support 8 bit data bit, 1 bit stop bit, no verification hardware flow control mode)
Platform: | Size: 452608 | Author: 寒山 | Hits:

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[VHDL-FPGA-Verilog] uart

[LabView] verilog-uart-master

[VHDL-FPGA-Verilog] uart_test

[Other] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Com Port] FPGA实现串口解析

[Embeded-SCM Develop] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[Windows Develop] UART

[VHDL-FPGA-Verilog] UART-master

[Other] Verilog_uart

[VHDL-FPGA-Verilog] UART1

[e-language] uart-master

[Com Port] uart

[VHDL-FPGA-Verilog] eetop.cn_uart 源码 (Verilog)

[Com Port] VERILOG_UART

[VHDL-FPGA-Verilog] UART

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